context: 2026-06-27 readiness engines committed + IE-priority decision

Merge Pi's parallel update (AIOS map done). Record dedup+verdict commits
(c07d054, 206bf71), auditor-fixed false-green holes, labABLE brief sent, and
the prioritization decision: Signal pauses at this checkpoint while Claude+Kisa
finish the Insight Engine to July 4; Pi advances Signal UX async.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

context/current-state.md

@@ -2,14 +2,15 @@ v:1
 
 # current-state
 
-ACTIVE: 2026-06-26 Pi session. STTIL AIOS architecture map DESIGNED and WRITTEN (STTIL-Vault/Projects/STTIL-AIOS-architecture-map.md, 338 lines, 10 sections). Claude SHIPPED readiness-model core engines (dedup + verdict) — additive only, not yet wired. Pi's AIOS map confirms Layers 1-3 are solid; readiness model is unblocked. See NEXT for remaining build steps.
+ACTIVE: 2026-06-27. Readiness-model core engines COMMITTED (additive, not yet wired): dedup foundation core/dedup.py (c07d054) + verdict engine core/readiness.py (206bf71); 73 tests green; both code-auditor-reviewed (HIGH config-surface false-green holes found + fixed). Pi's STTIL AIOS architecture map is DONE (STTIL-Vault/Projects/STTIL-AIOS-architecture-map.md, 338 lines). Pi briefed for the readiness worklist UX (STTIL-Vault/Projects/pi-readiness-ux-design-brief-2026-06-27.md). labABLE CRUSH brief SENT 2026-06-27. PRIORITIZATION: Signal active build PAUSES at this clean checkpoint; Claude + Kisa finish the Insight Engine to its July 4 deadline (separate lane/terminal); Pi advances the Signal UX design async.
 
-NEXT (in order): (1) Kisa: send the labABLE CRUSH brief + schedule follow-up call (staged at ~/Documents/labABLE/). (2) Claude: continue readiness-model build — rules-to-addressable-config (citation IDs), patient rollup, device-keyed override + recompute + rollup, require-plan-type enforcement + remove name-guesser/default in LIVE path. (3) Pi: design frontend nesting + "plan type needed" UX label mapping (Claude flagged this as a Pi task in readiness.py). (4) Claude: create signal-convex repo + build Phase 1 of Convex-Signal spike. (5) Claude: research-versioning Layer-1 + add signal/docs/ to scope.
+NEXT (in order): (1) Pi: readiness worklist UX design — brief staged 2026-06-27 (STTIL-Vault/Projects/pi-readiness-ux-design-brief-2026-06-27.md): label semantics, patient→device→doc nesting, "Plan Type Needed" state, plan-type value-mapping at import. (2) Claude (after Pi design + Kisa sign-off — BEHAVIOR CHANGE to live grading): patient rollup + WIRE readiness model into the live pipeline (orchestrate in api/main.py or a new module, NOT inside coverage_calculator — circular import) + rules-to-addressable-config (citation IDs) + remove live name-guesser/default path. (3) Kisa: schedule labABLE follow-up call (CRUSH brief SENT 2026-06-27). (4) Claude: signal-convex repo + Convex spike Phase 1. (5) Claude: research-versioning Layer-1 + add signal/docs/ to scope. NOTE: Signal active build PAUSED until the Insight Engine ships (~July 4 deadline).
 
 [AIOS build status] The map is written. Highest-impact build is the readiness model, NOT AIOS enhancements. AIOS Phase 1 items (reasoning frameworks, Playground, /board skill) are <5 hours total and optional until Signal has customer momentum.
 
 ## Decisions (last 8)
 
+- 2026-06-27 [CC]: Readiness engines COMMITTED — c07d054 (dedup foundation) + 206bf71 (verdict engine); code-auditor found + fixed HIGH config-surface false-green holes (a known plan missing from payer_rules.json no longer grades green; the green gate now checks every item); 73 tests green. Pi readiness-UX brief staged. labABLE CRUSH brief SENT. PRIORITIZATION DECISION (Kisa): Signal active build pauses at this checkpoint; Claude + Kisa finish the Insight Engine to its July 4 deadline (separate lane); Pi advances the Signal UX design async. Lanes-clear: one project per terminal/session.
 - 2026-06-26 [Pi]: STTIL AIOS architecture map DESIGNED and WRITTEN to STTIL-Vault/Projects/STTIL-AIOS-architecture-map.md (338 lines, 10 sections). 6-layer architecture with per-layer Have/Partial/Gap status, build sequence in 3 phases, and comparison to coach's framework. Kisa is ahead of coach's L2 AIOS in memory breadth, multi-model research, and cross-session state protocol. Highest-impact build remains the Signal readiness model.
 - 2026-06-26 [CC]: Readiness-model core engines SHIPPED — dedup.py (250 lines, 30 tests) + readiness.py (286 lines, 27 tests). All 57 tests green. Dedup key = (patient_id, device_type, DOS). Verdict engine kills the false green (required+absent blocks green, plan unknown = Plan Type Needed). Additive only, not yet wired into live pipeline. Remaining: rules-to-config, patient rollup, device override, plan-type enforcement, frontend nesting.
 - 2026-06-25 [CC]: labABLE call done (CRUSH/audit-readiness angle). CRUSH brief + verified, 3-model-cross-checked research (Opus agents, Sonnet 4.6, Perplexity Sonar) staged for Kisa to send (Projects/labABLE-CRUSH-brief-2026-06-25.md). Perplexity MCP fixed (BASE_URL=/chat/completions). OpenRouter `ask` multi-model CLI wired. Pi briefed to design the STTIL AIOS map. Display corruption diagnosed as macOS 26.0.1 GPU issue (fix = update to 26.5.1).
@@ -45,4 +46,4 @@ NEXT (in order): (1) Kisa: send the labABLE CRUSH brief + schedule follow-up cal
 
 State protocol: read = `git pull --rebase` then read this file (warn if Updated > 24h old); write = edit ACTIVE/NEXT, append one author-stamped decision, then commit + push. Full protocol in the `state-sync` skill. Detailed ship-status (what shipped / didn't / why) = docs/ship-status-ledger.md. TriLane = searchable archive, not live state.
 
-## Updated: 2026-06-26 (Pi: STTIL AIOS architecture map designed + written to file. CC: readiness-model core engines shipped (dedup + verdict, 57 tests green, additive not wired). State updated to reflect both milestones.)
+## Updated: 2026-06-27 (CC: readiness engines committed c07d054+206bf71, auditor-fixed HIGH false-green holes, 73 tests; Pi readiness-UX brief staged; labABLE brief sent. PRIORITIZATION: Signal paused at checkpoint, Claude+Kisa finish Insight Engine to July 4, Pi advances Signal UX async.)